The present invention relates to a CMOS amplifier circuit formed by a CMOS semiconductor process, and to an output circuit of a charge-coupled device (CCD) delay line which includes the CMOS amplifier circuit.
Recently, integrated circuit devices (ICs and LSICs) formed by a CMOS semiconductor process have been extensively employed because they have excellent characteristics. Namely, CMOS circuits have a wide operating voltage range and are low in power consumption. CMOS amplifier circuits formed by a CMOS semiconductor process are applied to internal signal amplifier circuits, output power amplifier circuits, and so forth.
A CMOS amplifier circuit AMP shown in FIG. 7 is known in the art. Specifically, the CMOS amplifier circuit is an active load type source-grounded inverting amplifier circuit. A P-channel MOS transistor Q.sub.1 serving as an active load has its gate and source electrodes connected together. An N-channel MOS transistor Q.sub.2 is connected between a high voltage source V.sub.CC and a low voltage source V.sub.EE (V.sub.CC &gt;V.sub.EE). A signal V.sub.G is applied to the gate electrode of the MOS transistor Q.sub.2 and subjected to inversion and amplification to provide an output signal V.sub.0 at the common connecting point of the transistors Q.sub.1 and Q.sub.2.
It is assumed that the mutual conductance of the MOS transistor Q.sub.1 is represented by g.sub.mL, the resistance between the drain and the source thereof is represented by r.sub.dsL, the mutual conductance of the MOS transistor Q.sub.2 is represented by g.sub.mD, and the resistance between the drain and the source thereof is represented by r.sub.dsD. Hence, the output impedance Z.sub.0 of the amplifier circuit is as follows: ##EQU1## The voltage amplification factor A.sub.V is as follows: EQU A.sub.V =V.sub.0 /V.sub.G =-g.sub.mD .times.Z.sub.0 ( 2)
In the amplifier circuit, the parallel resistance of r.sub.dsL and r.sub.dsD has the following relationship: EQU (r.sub.dsL .times.r.sub.dsD)/(r.sub.dsL +r.sub.dsD)&gt;1/g.sub.mL( 3)
Therefore, in above-described equation (2), the voltage amplification factor A.sub.V, can be rewritten as follows: EQU A.sub.V .apprxeq.-g.sub.mD /g.sub.mL ( 4)
The above-described CMOS amplifier circuit is advantageous over a source-grounded inverting amplifier circuit in that it can be lower in impedance and it can be miniaturized.
The signal V.sub.G applied to the gate electrode of the MOS transistor Q.sub.2 is generally supplied from a differential amplifier as shown in FIG. 7. The differential amplifier includes N-channel MOS transistors Q.sub.3 and Q.sub.4 forming a differential pair a constant current circuit I.sub.0, and P-channel MOS transistors Q.sub.5 and Q.sub.6 forming an active load. An input signal V.sub.I from- various circuits (not shown) is applied to the gate electrode of the MOS- transistor Q.sub.3.
The amplifier circuit can also be employed as a voltage follower circuit which has improved linearity with the output signal V.sub.0 fed back to the gate electrode of the MOS transistor Q.sub.4 on the non-inverting input side of the differential amplifier.
However, the above-described conventional amplifier circuit suffers from certain problems and disadvantages which are discussed below.
First, as shown in FIG. 8, the threshold voltage V.sub.th of the MOS transistor Q.sub.1 connected to the high voltage source V.sub.CC causes compression of the output DC dynamic range on the side of V.sub.CC.
Second, in the case where the CMOS amplifier circuit is used as a buffer amplifier where a plurality of circuits are connected to it in subsequent stages, it is desirable that the output impedance Z.sub.0 be low. However, since the voltage of the output signal V.sub.0 is increased with the decreasing voltage of the input signal V.sub.G of the MOS transistor Q.sub.2, the bias voltage V.sub.GS between the gate and the source of the MOS transistor Q.sub.1 is decreased, and the mutual conductance g.sub.mL is also decreased. Therefore, as is apparent from the above equations (2) and (4), as the mutual conductance g.sub.mL decreases, the output impedance Z.sub.0 increases. As the output impedance Z.sub.0 increases in this manner, the high-frequency cut-off frequency f.sub.H is decreased. As a result, the circuit may become unstable, resulting in undesirable oscillation.
Third, the capacitance between the gate and the drain of the MOS transistor Q.sub.1 forms a capacitive load on the MOS transistor Q.sub.2. Hence, the high-frequency cut-off frequency f.sub.H is lowered by the capacitive load, thus making it difficult to increase the bandwidth of the circuit.